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| PJSR70TB4 Very Low Capacitance Diode Array This diode array is configured to protect up to two high speed data transmission lines, used in Low Voltage Differential Signal (LVDS) ports. Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage events as electrostatic discharges. This configuration comes in the new SOT543 package, offering a significative printed circuit board space savings compared to the SOT143. SOT543 Package 4 3 1 2 SPECIFICATION FEATURES Maximum Capacitance of 1.0pF at 0Vdc 1MHz Line-to-Ground Maximum Leakage Current of 1.0A @ VRWM New SMT Package SOT543 IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact* 100% Tin Matte finish (LEAD-FREE PRODUCT) +VREF 4 Line1 3 APPLICATIONS USB 2.0 and Firewire Port Protection HDMI Version 1.3 DVI 1 2 Gnd Line2 MAXIMUM RATINGS Tj = 25C Unless otherwise noted Rating Peak Pulse Current (8/20s Waveform) Rectifier Repetitive Peak Reverse Voltage Operating Junction Temperature Range Storage Temperature Range Soldering Temperature, t max = 10s Symbol I PPM VRRM TJ Tstg TL Value 12 70 -55 to +125 -55 to +150 260 Units A V C C C Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected. 2/18/2009 Page 1 www.panjit.com PJSR70TB4 ELECTRICAL CHARACTERISTICS Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Diode Surge Forward Voltage (8/20s) Diode Surge Forward Voltage (8/20s) Diode Surge Forward Voltage (8/20s) Off State Capacitance Symbol V RWM VBR IR VFC VFC VFC CT I BR = 50A VR = 70V I pp = 1A I pp = 5A I pp = 12A 0 Vdc Bias f = 1MHz Between I/O Line and GND 0 Vdc Bias f = 1MHz Between I/O lines Tj = 25C unless otherwise noted Conditions Min Typical Max 70 85 1.0 2.0 7.0 12 0.8 0.5 1.0 0.6 Units V V A V V V pF pF 2/18/2009 Page 2 www.panjit.com PJSR70TB4 PACKAGE DIMENSIONS - SOT543 4 4 0.038 (1.0) APPLICATION EXAMPLE Vbus+ LVDS D+ DIC Controller 2/18/2009 Page 3 www.panjit.com |
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